1. Field of the Invention
The present invention relates to a method of fabricating a microelectronic device, and more particularly, to a method of fabricating a dual damascene interconnection of a microelectronic device.
2. Description of the Related Art
With rapid progress and development in the techniques available to produce high-speed, highly-integrated logic devices, new techniques for fabrication of miniaturized transistors have been developed. As the integration level of the transistors is increased, interconnections become smaller and smaller. As a result, the problem of interconnection delay becomes incrementally more serious, impeding the attainment of high-speed logic devices.
In view of the above, interconnections that employ copper having lower resistance and higher electromigration (EM) tolerance as an interconnection material, instead of an aluminum alloy, which have been conventionally and generally used in interconnecting large scale integrated (LSI) semiconductor devices, have been actively developed. However, copper is relatively difficult to etch and is prone to oxidation. Accordingly, a dual damascene process has been developed to form such a copper interconnection.
The dual damascene process includes forming a trench having an upper interconnection formed on an insulating layer, and a via that connects the upper interconnection to a lower interconnection or to a substrate, and filling the trench and the via with copper. The resulting structure is then planarized by a chemical mechanical polishing (CMP) process.
The dual damascene process is employed in forming bit lines or word lines in addition to metal wiring. In particular, in the dual damascene process, vias for connecting an upper metal wiring to a lower metal wiring in a multi-layered metal wiring structure, can also be formed at the same time. Further, the dual damascene process facilitates further processing because a step difference caused by the metal wiring is removed during the dual damascene process. Dual damascene processes can be roughly classified into a via-first process and a trench-first process. In the via-first process, a via is first formed by etching a dielectric by photography and etching, and a trench is then formed on top of the via by further etching of the dielectric. In the trench-first process, on the contrary, the trench is first formed and the via is then formed. Of the two, the via-first process has enjoyed more common use.
Hereinafter a conventional method of fabricating a dual damascene interconnection will be described with reference to FIGS. 1A through 2B.
FIGS. 1A and 1B are sectional views of stages in a conventional method of fabricating a dual damascene interconnection. In some conventional dual damascene processes, a hard mask is used as an etch mask when trench etch is performed to form the trench. Referring to FIG. 1A, a hard mask 150 defining a trench 170 is patterned on an intermetalic dielectric (IMD) layer 140. When the IMD layer 140 is dry etched using the hard mask 150 as an etch mask, the hard mask 150 may be partially etched due to bombardment of ions within plasma during the formation of the trench 170. The dry etch is actively performed especially at an edge portion (A shown in FIG. 1A) of the hard mask 150, which defines the resulting size of the trench 170, forming a profile with a rounded edge. As a result, the IMD layer 140 positioned below the edge portion A of the hard mask 150 corresponding to an upper portion of the trench 170 is also etched so that the profile has a rounded edge. The rounded profile causes the critical dimension (CD) of an interconnection to be reduced.
Referring to FIG. 1B, after forming the trench 170 in the IMD layer 140, an etch-back process 180 is commonly performed to remove the hard mask 150 and an etch stop layer 130 exposed through via 160. During the mechanical etch-back process 180, in addition to the hard mask 150 and the etch stop layer 130, the exposed portion of the IMD 140 (portion B shown in FIG. 1B) of the trench 170 is also etched, increasing the roundness of the profile. As a result, the CD of the resulting interconnection can be even further reduced. In FIGS. 1A and 1B, reference numerals 110 and 120 denote a substrate and a lower interconnection line, respectively.
FIG. 2A is a scanning electron microscope (SEM) photo of the sectional view shown in FIG. 1A, and FIG. 2B is a SEM photo of the section view shown in FIG. 1B. Referring to FIG. 2A, during dry etch for forming a trench, the hard mask 210 is etched, which leads to a rounded-edge profile, as shown. Referring to FIG. 2B, when etch-back is performed to remove the hard mask 210 shown in FIG. 2A and to remove etch stop layer 230 exposed through a via, etching is also performed at an upper edge portion 220 of the trench, which cause the profile to become even more rounded.
As described above, during the dry etch for forming the trench 170 and the etch-back process 180 for removing the hard mask 150 and the etch stop layer 130, the IMD layer 140 is partially etched, since etch selectivity of the IMD layer 140 with respect to the hard mask 150 is not high in the case of a mechanical etch using plasma. As a result, the width of the resulting trench 170 exceeds a threshold value, and therefore, the dimension of the trench 170 cannot be controlled accurately.
In this situation, the CD of the interconnection is reduced, which may result in an unwanted increase in leakage current or even potentially cause a short-circuit in the interconnection. To overcome these problems, after an interconnection material is formed in the via 160 and the trench 170, additional chemical-mechanical polishing (CMP) may be performed to planarize the device so that satisfactory CD may be secured for the interconnection. However, excessive CMP can cause overall fabrication time to increase, leading to low product yield and other undesired effects.